Implication-Based Gate-level Synthesis for Low-Power Topics: Technology-Independent, Combinational Logic Synthesis and Optimization

The paper presents a new logic optimization method of multi-level combinational CMOS circuits, which minimizes area and power. Present methods to reduce power on logic circuits apply functional methods like logic factorization on the Boolean networks. The method described here uses Boolean transformations that exploit implications at the gate-level based on both controllability and observabil-ity relationships. These transformations are novel and have not been explored for low power synthesis. It is observed that the average switching activity of lines in a circuit is the primary cause for power consumption. Restructuring the circuit based on the switching activity can signiicantly reduce the average power consumption in a circuit. New transformations are presented here, along with a new synthesis method to optimize both area and power. Our methods can also be applied as a pre-processing step before technology mapping. Experimental results show circuits synthesized by our method consume less power with a lesser area than those synthesized by SIS and HANNIBAL.